[11/2(수) 세미나 안내] High-speed Wireline Transceiver 설계_류효겸 상무 (삼성전자 Foundry IP개발팀)
- ice
- 조회수2077
- 2022-11-01
[11/2(수) 초청세미나 안내] High-speed Wireline Transceiver 설계
1. 제목: High-speed Wireline Transceiver 설계
2. 일시 및 장소: 11월 2일 수요일 16:30~18:30 (장소: 화학관 330102호실)
3. 발표자: 류효겸 상무 (삼성전자 Foundry IP개발팀)
4. 연사 약력:
Samsung Foundry, Hwaseong, Korea
2020 - Present Corporate Vice President
✓ In charge of high-speed interface IP design including serdes IP for ethernet/MPHY/PCIe, and memory interface IP
Broadcom, Irvine, CA
2012 - 2020 Principal Circuit Designer
✓ As a High-speed Serdes circuit designer, led RX and TX design in several projects using TSMC 28/20/16/7nm CMOS
process. Designed circuits, interacted with layout engineers, conducted design reviews, and led debugging process.
o Serdes analog design for a ADC/DSP based Coherent transceiver(64GS/s, 70GS/s, 90GS/s)
o Serdes analog design for a ADC/DSP based PAM-4 transceivers(56Gb/s, 112Gb/s)
o Serdes analog design for a mixed-signal PAM-4 transceivers(28Gb/s, 56Gb/s)
Intel, Hillsboro, OR
Jan. 2012 - Aug. 2012: Intern
✓ As an RF circuit design intern, designed and developed a Bluetooth and WiFi receiver chain, using TSMC 28nm
CMOS process. Designed the circuit, interacted with layout engineers, and performed design reviews.
Mediatek, Wilmington, MA
Jun. 2008 - Aug. 2008: Intern
✓ As a PLL circuit design intern, developed a behavioral model of PLL for GSM system and designed a charge pump
and DCO for PLL in UMC 65nm CMOS technology.
Alticast, Seoul, South Korea
May. 2002 - Dec. 2004: Software Designer
✓ As a JAVA software designer, developed a J2EE based server system for digital TV broadcasting system.
5. 초록: 고속 interface IP의 시장과 기술 trend에 대해 간략히 소개하고, serdes의 기본 개념을 설명한 후 현재 진행되고 있는 연구 내용을 소개한다.
이전 serdes에서 analog 영역이었던 많은 부분이 digital로 옮겨오면서 성능과 scalability가 크게 개선되는 것이 요즘 trend이다. 따라서 고속 interface IP의 발전을 이끌어낼 수 있도록 digital 분야에서 많은 연구가 필요하다.
추가 공지: Foundry 사업부 IP 개발팀 소개 및 채용 관련 Q&A 진행