스웨덴 Uppsala University의 박창현 교수님의 세미나가 11월 6일에 진행될 예정입니다. 박창현 교수님께서는 컴퓨터구조와 운영체제 분야에서 활발한 연구를 하고 계십니다.

관심 있는 학생 여러분들의 많은 참석 바랍니다.

■일시: 2025. 11. 6 (목요일) 10:00 ~ 11:00

■장소: 반도체관 400102호

■주제: “Second-level Caches: Not for Instructions”

■연사: Uppsala University, 박창현 교수

Chang Hyun Park is an assistant professor at the department of information technology, Uppsala University, Sweden. He researches computer architecture and systems, specifically focusing on the memory system and the virtual memory system. Chang Hyun received his PhD from KAIST where he researched improving the performance of the virtual memory system, specifically the TLB.

■ABSTRACT

Growing instruction footprints are straining processor front-ends, increasing fetch latency, and causing pipeline stalls. The universal approach to addressing this has been keeping instructions in each level of the cache hierarchy, but a plethora of more advanced techniques, ranging from instruction prefetching to prioritizing instruction cache-lines, have also been proposed to reduce instruction fetch latency.

In this work we identify a significant subset of benchmarks that exhibit an insensitivity to instruction fetch latency to the extent that we can take the opposite approach and explicitly bypass the L2 for instructions. While conventional wisdom suggests that this will hurt performance, our detailed analysis of 2120 traces finds that two factors mitigate this effect.

In this talk, I will go over our analysis that helps explain why bypassing the L2 for instructions results in performance gains for some workloads.

■HOST: 홍석인 교수 (전자전기컴퓨터공학과)