(Ph.D) Electrical Engineering, Seoul National University, Seoul, Korea, 2009.08
약력/경력
Senior Engineer, Semiconductor R&D Center, Samsung Electronics, 2009.09-2016.02.
Principal Engineer, Semiconductor R&D Center, Samsung Electronics, 2016.03-2017.08.
Assistant Professor, Konkuk University, 2017.09-2021.08
Associate Professor, Konkuk University, 2021.09-2023.08
Associate Professor, SungkyunKwan University, 2023.09-
학술지 논문
(2026)
Investigation of TMDC-based Impact-Ionization Field Effect Transistor (I2-FET) for Low Power Logic.
Results in Physics.
87,
1
(2026)
Investigation on α-particle-induced single event effects in AlGaN/GaN HEMTs: Bias, strike location, and trap effects.
AIP ADVANCES.
16,
6
(2026)
From Vulnerability to Robustness: Radiation‑Hard Isolation for BPR‑Enabled Stacked Nanosheet CFETs.
NUCLEAR ENGINEERING AND TECHNOLOGY.
58,
1
(2026)
3-Tier CFET 6T-SRAM with 2D-TMDs channels for Angstrom technology node.
SCIENTIFIC REPORTS.
16,
1
(2026)
Automated, physics-guided AI framework for asymmetry-aware ferroelectric compact models.
SCIENTIFIC REPORTS.
16,
1
(2026)
Hot carrier degradation in p-MOSFETs at extremely low to room temperatures (77-370 K).
SEMICONDUCTOR SCIENCE AND TECHNOLOGY.
41,
3
(2026)
Lateral Leakage Suppression Using H2 Plasma-Treated SiNx for High-Resolution Organic Displays.
IEEE ELECTRON DEVICE LETTERS.
47,
3
(2026)
Advances and Future Challenges in Monolithic 3D Integrated Logic, Power, and Optoelectronics Technologies for Tightly Interconnected Intelligent Systems.
ACS NANO.
20,
8
(2026)
Asymmetry-Aware Compact Modeling of Ferroelectric Devices for Circuit-Level Simulation.
ACS APPLIED ELECTRONIC MATERIALS.
8,
4
(2026)
Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash.
IEEE ACCESS.
14,
1
(2026)
Line-type tall via structures for CFET: superior scalability and manufacturability through gate extension reduction.
SEMICONDUCTOR SCIENCE AND TECHNOLOGY.
41,
1
(2025)
Impact of Interconnect on Ferroelectric FinFET-Based Logic-in-Memory Circuits at 3nm Technology Node.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
44,
12
(2025)
Via-Optimized CFET 6T SRAM: Performance, Stability, Manufacturability, and Scalability.
IEEE TRANSACTIONS ON ELECTRON DEVICES.
73,
1
(2025)
Novel vertical contact architecture for significantly reduced contact resistance in 2D nanosheet FETs.
NPJ 2D MATERIALS AND APPLICATIONS.
9,
1
(2025)
High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems.
NATURE COMMUNICATIONS.
16,
1
(2025)
Enhanced programming efficiency in vertical NAND flash using self-boosting hot carrier injection.
SCIENTIFIC REPORTS.
15,
1
(2025)
Thermal performance enhancement of complementary field-effect transistors via comparative analysis of power delivery structures.
JOURNAL OF APPLIED PHYSICS.
138,
14
(2025)
Enhancing memory performance in IGZO-based 2T0C DRAM through comparative analysis of CAA and GAA FET structures.
JOURNAL OF COMPUTATIONAL ELECTRONICS.
24,
6
(2025)
Area-Adjusted Comparison of BSPDN Interconnects in CFET: Superiority of Frontside Connection.
IEEE TRANSACTIONS ON ELECTRON DEVICES.
72,
11
(2025)
Investigation of Nanoscale Bonding-Based Complementary FETs.
IEEE TRANSACTIONS ON ELECTRON DEVICES.
72,
9
단행본
(2025)
태양광 모듈의 신뢰성 분석.
디자인21.
공동
특허/프로그램
Stack structure and manufacturing method thereof, capacitor using the same, transistor using the same, dye-sensitized solar cell using the same, and architectural film for window glass coating using the same.
US20250185407A1.
20250605.
미국
학술회의논문
(2025)
FuncFlow: A Generative Neural Operator Using Diffusion Model for Simulation Augmentation.
2025 International Compact Modeling Conference (ICMC).
미국
(2025)
Large Pre-Trained Model Approach for Efficient Design Technology CO-Optimization.
2025 International Compact Modeling Conference (ICMC).
미국
(2025)
Unified Dynamic Library: Neural Network-Based Compact Modeling for Enhanced Efficiency.
2025 International Compact Modeling Conference (ICMC).
미국
(2025)
Electro-Thermal Co-Optimization of 2D Channel-Based Complementary FET Structures.
대한전자공학회 2025년도 하계종합학술대회.
대한민국
(2025)
Optimizing Wordline Design for Enhanced Erase Characteristics in Vertical NAND Flash Memory.
대한전자공학회 2025년도 하계종합학술대회.
대한민국
(2025)
Optimization of TSV-Induced Stress Using a Slanted Profile in a Backside TSV Process.
International Conference on Electronics, Information, and Communication (ICEIC).
미국
(2025)
Optimization of TSV Induced Stress Using a Slanted Profile in a Backside TSV Process.
2025 International Conference on Electronics, Information, and Communication (ICEIC).
일본
(2025)
SRAM bitcell Design and Characteristics in the three-stacked CFET structure for CMOS scaling.
2025 International Conference on Electronics, Information, and Communication (ICEIC).
일본
(2024)
ANN을 활용한 14nm FinFET BSIM 모델 파라미터 추출.
하계학술대회.
대한민국
(2024)
AlGaN/GaN HEMT 소자의 Contact 길이 변화 및 Backside Via 구조 적용에 따른 열 저항의 변화에 관한 3D 시뮬레이션 연구.
하계학술대회.
대한민국
(2024)
HZO기반 FeRAM 메모리 어레이 교란성 분석.
하계학술대회.
대한민국
(2024)
Optimal data distribution in FeFET-based computing-in-memory macros.
IEEE International Symposium on Circuits and Systems (ISCAS).
미국
(2024)
Comparative TCAD Analysis of Single-Event Transients in Forksheet FETs and Bottom Dielectric Isolation-Integrated Forksheet FETs.
한국반도체학술대회.
대한민국
(2023)
DAT: Leveraging Device-Specific Noise for Efficient and Robust AI Training in ReRAM-based Systems.
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
미국
(2023)
FlowSim: An Invertible Generative Network for Efficient Statistical Analysis under Process Variations.
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
미국
